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rev. a a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 adv7304a/adv7305a multiformat sd, progressive scan/hdtv video encoder with six nsv 14-bit dacs nsv (noise shaped video) is a trademark of analog devices, inc. * adv7304a only features high definition input formats ycrcb compliant to smpte293m (525 p), itu-r.bt1358 (625 p), smpte274m (1080 i), smpte296m (720 p), and any other high definition standard using async timing mode rgb in 3 10-bit 4:4:4 format bta t-1004 edtv2 525 p parallel high definition output formats (525 p/625 p/720 p/1080 i) yprpb progressive scan (eia-770.1, eia-770.2) yprpb hdtv (eia 770.3) rgb + h/v (hdtv 5-wire format) cgms-a (720 p/1080 i) macrovision rev 1.0 (525 p/625 p)* cgms-a (525 p) standard definition input formats ccir-656 4:2:2 8-/10-bit parallel input ccir-601 4:2:2 16-/20-bit parallel input standard definition output formats composite ntsc m, n; pal m, n, b, d, g, h, i, pal-60 smpte170m ntsc compatible composite video itu-r.bt470 pal compatible composite video s-video (y/c) euroscart rgb component yuv (betacam, mii, smpte/ebu n10) macrovision rev 7.1* cgms/wss closed captioning general features simultaneous sd and hd inputs and outputs oversampling (108 mhz/148.5 mhz) on-board voltage reference 6 nsv precision video 14-bit - dacs 2-wire serial mpu interface dual i/o supply 2.5 v/3.3 v operation analog and digital supply 2.5 v on-board pll 64-lqfp package lead-free product applications high end dvd players sd/program scan/hdtv display devices sd/program scan/hdtv set-top boxes sd/hdtv studio equipment professional video equipment simplified functional block diagram s9?0 y9?0 c9?0 s_h sync s_v sync s_blank p_h sync p_v sync p_blank clkin_a clkin_b d e m u x timing generator pll o v e r s a m p l i n g i 2 c interface d e m u x standard definition control block color control brightness dnr gamma programmable filters sd test pattern high definition control block hd test pattern color control adaptive filter ctrl sharpness filter programmable rgb matrix 14-bit dac 14-bit dac 14-bit dac 14-bit dac 14-bit dac 14-bit dac adv7304a/ adv7305a general description the adv7304a/adv7305a is a high speed, digital-to-analog encoder on a single monolithic chip. it includes six high speed video d/a converters with ttl compatible inputs. the adv7304a/adv7305a has three separate 10-bit wide input ports that accept data in high definition and/or standard defini- tion video format. for all standards, external horizontal, vertical, and blanking signals, or eav/sav timing codes, control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals.
rev. a adv7304a/adv7305a ?2? fsc modulation s_hsync s_vsync s_blank clkin_a p_hsync p_vsync p_blank clkin_b hd pixel input sd pixel input de- inter- leave y cb cr test pa ttern sharpness and adaptive filter control y color cr color cb color 4:2:2 to 4:4:4 timing generator timing generator de- inter- leave y cb cr test pa ttern dnr gamma color control sync inser- tion clock control and pll 2 o ver- sampling uv ssaf v u ps 4 hdtv 2 rgb matrix sd 8 luma and chroma filters cgms wss dac dac dac dac dac dac figure 1. functional block diagram detailed features high definition programmable features (720 p/1080 i) 2 oversampling (148.5 mhz) internal test pattern generator (color hatch, black bar, flat field/frame) fully programmable ycrcb to rgb matrix gamma correction programmable adaptive filter control programmable sharpness filter control cgms-a (720 p/1080 i) high definition programmable features (525 p/625 p) 4 oversampling (108 mhz output) internal test pattern generator (color hatch, black bar, flat frame) individual y and prpb output delay gamma correction programmable adaptive filter control fully programmable ycrcb to rgb matrix undershoot limiter terms used in this data sheet sd standard definition video, conforming to itu-r.bt601/itu-r.bt656. hd high definition video, i.e., progressive scan or hdtv. ps progressive scan video, conforming to smpte293m or itu-r.bt1358. macrovision rev 1.0 (525 p/625 p)* cgms-a (525 p) standard definition programmable features 8 oversampling (108 mhz) internal test pattern generator (color bars, black bar) controlled edge rates for sync, active video individual y and uv output delay gamma correction digital noise reduction multiple chroma and luma filters luma-ssaf? filter with programmable gain/ attenuation uv ssaf separate pedestal control on component and composite/s-video outputs vcr ff/rw sync mode macrovision rev 7.1* cgms/wss closed captioning ssaf is a trademark of analog devices, inc. * adv7304a only hdtv high definition television video, conforming to smpte274m or smpte296m. ycrcb sd or hd component digital video. yprpb hd component analog video. yuv sd component analog video.
rev. a ?3? adv7304a/adv7305aespecifications parameter min typ max unit test conditions static performance 1 resolution 14 bits integral nonlinearity + = = = = ] 52 ma ps only [4 ] 84 ma hdtv only [2 ] 90 110 ma sd and ps 99 ma sd [8 ] and hdtv 108 ma sd and hdtv [2 ] i dd_io 0.2 ma i aa 5,6 70 75 ma sleep mode i dd 130 + = ( = = = = = = ( ? ? ) )
rev. a ?4? adv7304a/adv7305a dynamic specifications parameter min typ max unit test conditions progressive scan mode luma bandwidth 12.5 mhz chroma bandwidth 5.8 mhz snr 64 db luma ramp unweighted snr 82 db flat field up to 5 mhz snr 79 db flat field full bandwidth hdtv mode luma bandwidth 30 mhz chroma bandwidth 13.75 mhz snr 64 db luma ramp unweighted snr 82 db flat field up to 5 mhz snr 79 db flat field full bandwidth standard definition mode hue accuracy 0.6 degrees color saturation accuracy 0.5 % chroma nonlinear gain ( = = = = = = ( ? ? ) )
rev. a adv7304a/adv7305a ?5? timing specifications parameter min typ max unit test conditions mpu port 1 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 ( ) ( ) ( ) reset l t anal tpts a s clck cntrl an pel prt clk h p s clk h htv a c h t c l t s t h t a t h t p s ] 62.5 clkcycles sd [8 ] 66.5 clkcycles sd component filter [8 ] 33 clkcycles ps [1 ], hd [1 ], async timing mode 43.5 clkcycles ps [4 ] 36 clkcycles hd [2 ] notes 1 guaranteed by characterization. 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition. 3 data: c[9:0]; s[9:0]; y[9:0] control: p_hsync p_ vsync p_blank s_hsync s_vsync s_blank s v aa v v v v _ v v v re v r set r la t n t a c c
rev. a adv7304a/adv7305a ?6? t 9 t 11 clkin_a c9ec0 t 10 t 12 p_hsync , p_vsync , p_blank cb0 cr0 cb2 cr2 cb4 cr4 control i/ps y0 y1 y2 y3 y4 y5 y9ey0 t 14 control o/ps s_hsync , s_vsync t 13 t 9 = clock high time, t 10 = clock low time, t 11 = data setup time, t 12 = data hold time figure 2. hd 4:2:2 input data format timing diagram, input mode: ps input only, hdtv input only (input mode at subaddress 01h = 001 or 010) t 9 t 11 t 10 t 12 t 13 t 14 clkin_a c9ec0 p_hsync , p_vsync , p_blank control i/ps y9ey0 control o/ps s_hsync , s_vsync t 9 = clock high time, t 10 = clock low time, t 11 = data setup time, t 12 = data hold time s9es0 y0 y1 y2 yxxx yxxx cb0 cb1 cb2 cb3 cbxxx cbxxx cr0 cr1 cr2 cr3 crxxx crxxx figure 3. hd 4:4:4 ycrcb input data format timing diagram, input mode: ps input only, hdtv input only (input mode at subaddress 01h = 001 or 010)
rev. a adv7304a/adv7305a ?7? t 9 t 11 t 10 t 12 t 13 t 14 clkin_a c9ec0 p_hsync , p_vsync , p_blank control i/ps y9ey0 control o/ps s_hsync , s_vsync t 9 = clock high time, t 10 = clock low time, t 11 = data setup time, t 12 = data hold time s9es0 g0 g1 g2 gxxx gxxx b0 b1 b2 b3 bxxx bxxx r0 r1 r2 g3 rxxx rxxx figure 4. hd 4:4:4 rgb input data format timing diagram, hd rgb input enabled (input mode at subaddress 01h = 001 or 010) t 9 t 11 t 10 t 12 t 11 t 12 t 13 t 14 clkin_b y9ey0 p_hsync , p_vsync , p_blank control i/ps control o/ps s_hsync , s_vsync t 9 = clock high time, t 10 = clock low time, t 11 = data setup time, t 12 = data hold time cb0 y0 cr0 y1 crxxx yxxx figure 5. ps 4:2:2 1 10-bit interleaved @ 27 mhz, input mode: ps input only (input mode at subaddress 01h = 100)
rev. a adv7304a/adv7305a ?8? t 9 t 11 t 10 t 12 cb0 y0 cr0 y1 crxxx yxxx t 14 t 13 clkin_a y9ey0 p_hsync , p_vsync , p_blank control i/ps control o/ps s_hsync , s_vsync t 9 = clock high time, t 10 = clock low time, t 11 = data setup time, t 12 = data hold time figure 6. ps 4:2:2 1 10-bit interleaved @ 54 mhz, input mode: ps 54 mhz input (input mode at subaddress 01h = 111) t 9 t 11 t 10 t 12 cb y cr y cb y t 13 t 14 clkin_a s9es2 s_hsync , s_vsync , s_blank control i/ps control o/ps s_hsync , s_vsync in slave mode in master/slave mode with eav/sav figure 7. 8-bit sd pixel input timing diagram, input mode: sd input only (input mode at subaddress 01h = 000)
rev. a adv7304a/adv7305a ?9? t 9 t 11 clkin_a @ 27mhz s9es2 t 10 t 12 s_hsync , s_vsync , s_blank t 13 t 14 control i/ps control o/ps s_hsync , s_vsync y9ey2 in slave mode in master/slave mode with eav/sav cb0 cr0 cb2 cr2 y0 y1 y2 y3 figure 8. 16-bit sd pixel input timing diagram, input mode: sd input only (input mode at subaddress 01h = 000) t 9 t 11 t 10 t 12 cb0 cr0 cb2 cr2 cb4 cr4 y0 y1 y2 y3 y4 y5 cb0 y0 cr0 y1 cb1 y2 t 9 t 10 t 11 t 12 hd input sd input s9es0 s_hsync , s_vsync , s_blank control i/ps clkin_a clkin_b y9ey0 control i/ps p_hsync , p_vsync , p_blank c9ec0 figure 9. sd and hd simultaneous input, input mode: sd and ps 20-bit or sd and hdtv (input mode at subaddress 01h = 011, 101, or 110)
rev. a adv7304a/adv7305a ?10? s9es0 cb0 y0 cr0 y1 cb1 y2 s_hsync , s_vsync , s_blank control i/ps clkin_a t 9 t 10 t 11 t 12 sd input t 9 t 11 clkin_b y9ey0 t 10 t 12 t 11 t 12 control i/ps p_hsync , p_vsync , p_blank ps input crxxx yxxx cb0 y0 cr0 y1 figure 10. sd and hd simultaneous input, input mode: sd and ps 10-bit (input mode at subaddress 01h = 100) p_hsync p_vsync p_blank y9ey0 cb y cr y b a a = 32 clkcycles for 525p a = 24 clkcycles for 625p as recommended by standard b(min) = 244 clkcycles for 525p b(min) = 264 clkcycles for 625p figure 11. ps 4:2:2 1 10-bit interleaved @ 54 mhz input timing diagram
rev. a adv7304a/adv7305a ?11? p_hsync p_vsync p_blank y9ey0 y0 y1 y2 y3 cr0 cr1 cr2 cr3 cb0 cb1 cb2 cb3 b a a = 16 clkcycles for 525p a = 12 clkcycles for 626p a = 44 clkcycles for 1080i a = 70 clkcycles for 720p as recommended by standard s9es0 c9ec0 b(min) = 122 clkcycles for 525p b(min) = 132 clkcycles for 625p b(min) = 236 clkcycles for 1080i b(min) = 300 clkcycles for 720p figure 12. hd input timing diagram h sync field b lank pixel data pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y figure 13. sd timing input for timing mode 1 t 3 t 1 t 6 t 2 t 7 t 5 t 3 t 4 t 8 sda sclk figure 14. mpu port timing diagram
rev. a adv7304a/adv7305a ?2 absolute maximum ratings * v aa to agnd . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to ?.3 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to ?.3 v v dd_io to io_gnd . . . . . . . . . . . . . ?.3 v to v dd_io + 0.3 v ambient operating temperature (t a ) . . . . . . . 0 c to +70 c storage temperature (t s ) . . . . . . . . . . . . . . 65 c to +150 c infrared reflow soldering (20 sec) . . . . . . . . . . . . . . . . 260 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin 1 identifier top view (not to scale) v dd_io 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 y0 y1 y2 y3 y4 y5 y6 y7 v dd dgnd y8 y9 c0 c1 c2 s_blank r set1 v ref comp1 dac a dac b dac c v aa a gnd dac d dac e dac f comp2 r set2 ext_lf reset c3 c4 i 2 c alsb sda sclk p_hsync p_vsync p_blank c5 c6 c7 c8 c9 rt c_scr_tr clkin_a gnd_io clkn_b s9 s8 s7 s6 s5 dgnd v dd s4 s3 s2 s1 s0 s_hsync s_vsync adv7304a/adv7305a ordering guide model package description package option adv7304akst plastic quad flatpack st-64b ADV7305AKST plastic quad flatpack st-64b pin function descriptions pin no. mnemonic input/output function 1v dd_io pp ower supply for digital inputs and outputs 2?, 12, 13 y0?9 i 10-bit progressive scan/hdtv input port for y data. the lsbs are set up on pins y0 and y1. in default mode, the input on this port is output on dac d. 10, 56 v dd pd igital power supply 11, 57 dgnd g digital ground the adv7304a/adv7305a is a lead-free environmentally friendly product. it is manufactured using the most up-to-date materials and processes. the coating on the leads of each device is 100% pure tin electroplate. the device is suitable for lead-free applications and is able to withstand surface-mount soldering up to 255 c ( 5 c). in addition, it is backward compatible with conventional tin-lead soldering processes. this means that the electroplated tin coating can be soldered with tin-lead solder pastes at con ventional reflow temperatures of 220 c to 235 c. thermal characteristics jc = 11?/w ja = 47?/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7304a/adv7305a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a adv7304a/adv7305a ?13? pin no. mnemonic input/output function 14e18, 26e30 c0ec9 i 10-bit progressive scan/hdtv input port for crcb color data in 4:2:2 input mode. in 4:4:4 input mode, this input port is used for the cb (blue/u) data. the lsbs are set up on pins c0 and c1. in default mode, the input on this port is output on dac e. 19 i 2 ci this input pin must be tied high (v dd_io ) for the adv7304a/adv7305a to interface over the i 2 c port. 20 alsb i/o ttl address input. this signal sets up the lsb of the mpu address. when this pin is tied low, the i 2 c filter is activated, which reduces noise on the i 2 c interface. 21 sda i/o mpu port serial data input/output 22 sclk i mpu port serial interface clock input 23 p_hsync v h s c s h s s sh h p_vsync v v s c s h s s sh h p_blank v b c s h s s sh h rtc_scr_tr r c rtc t r s r clkn_a p c h s reset t ava ava r et_l e l pll r set a ? () () () ( ) s_blank v b c s s s_vsync v v c s s s vsync s hsync s s h s_hsync v h c s s s hsync h hsync s s h ss b s p p shtv p c rv c t lsb p s s ac clkn_b p c r h p s h h htv t s sh n_
rev. a adv7304a/adv7305a ?14? mpu port description the adv7304a/adv7305a supports a 2-wire serial (i 2 c com- patible) microprocessor bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (sclk), carry infor- mation between any device connected to the bus. each slave device is recognized by a unique address. the adv7304a/ adv7305a has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figures 15 and 16. the lsb sets either a read or write operation. logic level 1 corresponds to a read operation, while logic level 0 corresponds to a write operation. a1 is set by setting the alsb pin of the adv7304a/adv7305a to logic level 0 or logic level 1. when alsb is set to 1, there is greater input bandwidth on the i 2 c lines, which allows high speed data transfers on this bus. when alsb is set to 0, there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal con- troller. this mode is recommended for noisy systems. 1 1 0 1 0 1 a1 x address control set up by alsb read/write control 0 write 1 read figure 15. adv7304a slave address = d4h 0 1 0 1 0 1 a1 x address control set up by alsb read/write control 0 write 1 read figure 16. adv7305a slave address = 54h to control the various devices on the bus, the following protocol must be followed. first, the master initiates a data transfer by estab- lishing a start condition, defined by a high-to-low transition on sda, while sclk remains high. this indicates that an address/ data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w ss ssc w s s vv s w s sc vv s w vv vv s vv s scc s w c sss c c sp s p
rev. a adv7304a/adv7305a ?15? register accesses the mpu can write to or read from all of the registers of the adv7304a/adv7305a except the subaddress registers that are write-only registers. the subaddress register determines which register the next read or write operation accesses. all communica- tions with the part through the bus start with an access to the s ubaddress register. then a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following section describes the functionality of each regis- ter. all registers can be read from as well as written to unless otherwise stated. subaddress register (sr7esr0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. register select (sr7esr0) these bits are set up to point to the required starting address. write sequence read sequence s slave addr a(s) sub addr a(s) data a(s) data a(s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data data a(m) a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 figure 18. read and write sequence
rev. a adv7304a/adv7305a ?16? table i. power mode register subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 00h power mode register sleep mode 1 0 sleep mode off 1 sleep mode on pll and oversampling control 2 0 pll on 1 pll off dac f: power on/off 0 dac f off 1da c f o n da c e: power o n /off 0da c e off 1 dac e on dac d: power on/off 0 dac d off 1 dac d on dac c: power on/off 0 dac c off 1 dac c on dac b: power on/off 0 dac b off 1 dac b on dac a: power on/off 0 dac a off 1 dac a on fch notes 1 when enabled, the current consumption is reduced to () () ( ) ( )
rev. a adv7304a/adv7305a ?17? table iii. mode register subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting reset 02h mode register 0 reserved 0 0 zero must be written to these bits. 20h 0d isabled 1 enabled. 0x11h, bit 2 must also be enabled. 0 disable programmable rgb matrix 1 enable programmable rgb matrix 0n o sync 1 sync on all rgb out p uts 0 rgb component out p uts 1y uv component out p uts 0 no sync output 1 output sd syncs on s_hsync s_vsync n sync h sync s_hsync s_vsync rb lsb y rb lsb rv lsb b lsb v lsb rb b y e rb b e rb b v rb b b rb b rv c a r b r c r r e r r s sync h sync t p b b rb sync rb rbyv
rev. a adv7304a/adv7305a ?18? table iv. hd mode register subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 10h hd mode register 1 00 eia770.2 output 00h 01 eia770.1 output 10 output levels for full input range 11 reserved 00 hsync vsync b lank eavsav c a t r blank a h blank a l h r p v p v r h t p h t p h e re re re h r e c c c c c c c c c c c c c c c c c c c c e h y e hsync h c e hsync h cs h cs crc h c s h s h h h blank p h h t p h h vb h l h s h t p e h p v
rev. a adv7304a/adv7305a ?19? table iv. hd mode register (continued) subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting reset 13h hd mode register 4 0 cb after falling e dge o f h s y nc c e hsync r b b e r h c ssa e h c h b e h r a h h r r h rb e h s pp e h c ac s ac e p ac p ac p ac e p h c ab c a c b h c e e h a a b h a e e s ac e h h cc s c ntes eavsav ps 10-bit interleaved mode at 54 mhz. 2 4:2:2 input format only 3 4:4:4 input format only
rev. a adv7304a/adv7305a ?20? table v. register settings subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 16h hd y color xxxxxxxxy color value a0h 17h hd cr col or xxxxxxxxcr color value 80h 18h hd cb col or xxxxxxxxcb color value 80h 19h reserved 00h 1ah reserved 00h 1bh reserved 00h 1ch reserved 00h 1dh reserved 00h 1eh reserved 00h 1fh reserved 00h 20h 0000 gain a = 0 0001 gain a = +1 0111 gain a = +7 1000 gain a = e8 1111 gain a = e1 0000 gain b = 0 0001 gain b = +1 0111 gain b = +7 1000 gain b = e8 1111 gain b = e1 21h hd cgms data 0 hd cgms data bits 0000c19c18c17c16 cgms 19e16 00h 22h hd cgms data 1 hd cgms data bits c15 c14 c13 c12 c11 c10 c9 c8 cgms 15e8 00h 23h hd cgms data 2 hd cgms data bits c7 c6 c5 c4 c3 c2 c1 c0 cgms 7e0 00h 24h hd gamma a hd gamma curve a data points xxxxxxxxa0 00h 25h hd gamma a hd gamma curve a data points xxxxxxxxa1 00h 26h hd gamma a hd gamma curve a data points xxxxxxxxa2 00h 27h hd gamma a hd gamma curve a data points xxxxxxxxa3 00h 28h hd gamma a hd gamma curve a data points xxxxxxxxa4 00h 29h hd gamma a hd gamma curve a data points xxxxxxxxa5 00h 2ah hd gamma a hd gamma curve a data points xxxxxxxxa6 00h 2bh hd gamma a hd gamma curve a data points xxxxxxxxa7 00h 2ch hd gamma a hd gamma curve a data points xxxxxxxxa8 00h 2dh hd gamma a hd gamma curve a data points xxxxxxxxa9 00h 2eh hd gamma b hd gamma curve b data points xxxxxxxxb0 00h 2fh hd gamma b hd gamma curve b data points xxxxxxxxb1 00h 30h hd gamma b hd gamma curve b data points xxxxxxxxb2 00h 31h hd gamma b hd gamma curve b data points xxxxxxxxb3 00h 32h hd gamma b hd gamma curve b data points xxxxxxxxb4 00h 33h hd gamma b hd gamma curve b data points xxxxxxxxb5 00h 34h hd gamma b hd gamma curve b data points xxxxxxxxb6 00h hd sharpness filter gain hd sharpness filter gain value a hd sharpness filter gain value b 00h
rev. a adv7304a/adv7305a ?21? table vi. hd adaptive filters subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0r egister setting reset 38h 0000 gain a = 0 0001 gain a = +1 0111 gain a = +7 1000 gain a = e8 1111 gain a = e1 0000 gain b = 0 0001 gain b = +1 0111 gain b = +7 1000 gain b = e8 1111 gain b = e1 39h 0000 gain a = 0 0001 gain a = +1 0111 gain a = +7 1000 gain a = e8 1111 gain a = e1 0000 gain b = 0 0001 gain b = +1 0111 gain b = +7 1000 gain b = e8 1111 gain b = e1 3ah 0000 gain a = 0 0001 gain a = +1 0111 gain a = +7 1000 gain a = e8 1111 gain a = e1 0000 gain b = 0 0001 gain b = +1 0111 gain b = +7 1000 gain b = e8 1111 gain b = e1 3bh hd adaptive filter threshold a hd adaptive filter threshold a value xxxxxxxx threshold a 00hex 3ch hd adaptive filter threshold b hd adaptive filter threshold b value xxxxxxxx threshold b 00hex 3dh hd adaptive filter threshold c hd adaptive filter threshold c value xxxxxxxx threshold c 00hex hd adaptive filter gain 3 value b hd adaptive filter gain 2 value a hd adaptive filter gain 2 value b hd adaptive filter gain 1 hd adaptive filter gain 2 hd adaptive filter gain 3 00hex 00hex 00hex hd adaptive filter gain 1 value b hd adaptive filter gain 1 value a hd adaptive filter gain 3 value a
rev. a adv7304a/adv7305a ?22? table vii. sd mode registers subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 3eh reserved 00h 3fh reserved 00h 40h sd mode register 0 00 ntsc 01 pal b, d, g, h, i 10 pal m 11 pal n 000 lpf ntsc 001 lpf pal 010 notch ntsc 011 notch pal 100 ssaf luma 101 luma cif 110 luma qcif 111 reserved 000 1. 3 mhz 001 0.65 mhz 010 1. 0 mhz 011 2. 0 mhz 100 reserved 101 chroma cif 110 chroma qcif 111 3. 0 mhz 41h reserved 00h 42h sd mode register 1 0 disabled 1 enabled 0 dac a, b, c: cvbs, l, c; dac d, e, f: gbr or yuv 1 dac a, b, c: gbr or yuv; dac d, e, f: cvbs, l, c 0 swap dac a and dac d out p uts 1 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 00h 08h sd pixel data valid sd active video edge sd pedestal sd square pixel sd vcr ff/r w s s s s l s c s ac s v ssa s ac
rev. a adv7304a/adv7305a ?23? subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0r egister setting reset 43h sd mode register 2 sd pedestal yuv output 0 no pedestal on yuv 1 7.5 ire pedestal on yuv sd output levels y 0 y = 700 mv/300 mv 1y = 714 mv/286 mv sd output levels uv 0 0 700 mv p-p [pal]; 1000 mv p-p [ntsc] 01 700 mv p-p 10 1000 mv p-p 11 648 mv p-p sd vbi open 0 d isabled 1 enabled 00 cc disabled 01 cc on odd field only 10 cc on even field onl y 11 cc on both fields 1 reserved 0d isabled 1 vsync = 2.5 lines [pal]; vsync = 3 lines [ ntsc ] 00 genlock disabled 01 subcarrier reset 10 timing reset 11 rtc enabled 0 720 pixels 1 710 (ntsc); 702 ( pal ) 0 chroma enabled 1 chroma disabled 0 enabled 1d isabled 0d isabled 1 enabled reserved 0 zero must be written to this bit. 45h reserved 00h 46h reserved 00h 0d isabled 1 enabled 0d isabled 1 enabled 0d isabled 1 enabled 0d isabled 1 enabled 0d isabled 1 enabled reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. 00h sd mode register 3 sd rtc/tr/scr sd vsync-3h 00h 00h sd mode register 4 47h sd luma ssaf gain sd brightness sd hue adjust sd y scale sd uv scale sd cc field control 44h sd active video length sd chroma sd burst sd color bars table vii. sd mode registers (continued)
rev. a adv7304a/adv7305a ?24? table vii. sd mode registers (continued) subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. 00h 0 disabled 1 enabled 00 8-bit input 01 16-bit input 10 10-bit input 11 20-bit input 0 disabled 1 enabled 0 disabled 1 enabled 0 gamma curve a 1 gamma curve b 00 disabled 01 e11 ire 10 e6 ire 11 e1.5 ire 0 disabled 1 enabled 0 disabled 1 enabled 00 disabled 01 4 clock cycles 10 8 clock cycles 11 reserved reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. sd double buffering sd mode register 5 48h sd gamma control sd gamma curve sd digital noise reduction sd input format 00h 49h sd mode register 6 sd undershoot limiter sd black burst output on dac y sd chroma delay sd black burst output on dac luma * for more detail, see input and output configuration section.
rev. a adv7304a/adv7305a ?25? table viii. sd registers subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 4ah sd timing register 0 sd slave/master mode 0 slave mode 1 master mode sd timing mode 0 0 mode 0 01 mode 1 10 mode 2 11 m o d e 3 sd blank e s l n c c c c c c s l v re re s t r a s b s t r t c c t c c t c c t c c t c c t c c t c c t c c t t t t c c c c c c c c c c c c c c c c c s sc r s b s sc r s b c e s sc r s b s sc r s b s sc p s p b s c c e e e b s c c e e e b s c c b s c c b s p r p s p r p s p r p e s p r p e s s hsync vsync hsync p a s hsync vsync r e vsync w s hsync w
rev. a adv7304a/adv7305a ?26? table viii. sd registers (continued) subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 59h sd cgms/wss 0 sd cgms data 19 18 17 16 cgms data bits c19ec16 00h sd cgms crc 0 disabled 1 enabled sd cgms on odd fields 0 disabled 1 enabled sd cgms on even fields 0 disabled 1 enabled sd w ss 0 disabled 1 enabled 5ah sd cgms/wss 1 sd cgms/wss data 13 12 11 10 9 8 cgms data bits c13ec8 or wss data bits c13ec8 00h 15 14 cgms data bits c15ec14 5bh sd cgms/wss 2 sd cgms/wss data 76543210 cgms/wss data bits c7ec0 00h 5ch sd lsb register sd lsb for y scale value x x sd y scale bits 1e0 sd lsb for u scale value x x sd u scale bits 1e0 sd lsb for v scale value x x sd v scale bits 1e0 sd lsb for f sc phase x x subcarrier phase bits 1e0 5dh sd y scale register sd y scale value xxxxxxxxsd y scale bits 7e2 00h 5eh sd v scale register sd v scale value xxxxxxxxsd v scale bits 7e2 00h 5fh sd u scale register sd u scale value xxxxxxxxsd u scale bits 7e2 00h 60h sd hue register sd hue adjust value xxxxxxxxsd hue adjust bits 7e0 00h 61h sd brightness/wss sd brightness value xxxxxxxsd bright ness bits 6e0 sd blank wss data * 0 disabled 1 enabled 62h sd luma ssaf sd luma ssaf gain/attenuation 00000000e4 db 000001100 db 00001100+4 db 63h sd dnr 0 coring gain border 0000no gain 0001 +1/16 (e1/8 in dnr mode ) 0010 +2/16 (e2/8 in dnr mode ) 0011 +3/16 (e3/8 in dnr mode ) 0100 +4/16 (e4/8 in dnr mode ) 0101 +5/16 (e5/8 in dnr mode ) 0110 +6/16 (e6/8 in dnr mode ) 0111 +7/16 (e7/8 in dnr mode ) 1000 +8/16 (e1 in dnr mode ) coring gain data 0000 no gain 0001 +1/16 (e1/8 in dnr mode ) 0010 +2/16 (e2/8 in dnr mode ) 0011 +3/16 (e3/8 in dnr mode ) 0100 +4/16 (e4/8 in dnr mode ) 0101 +5/16 (e5/8 in dnr mode ) 0110 +6/16 (e6/8 in dnr mode ) 0111 +7/16 (e7/8 in dnr mode ) 1000 +8/16 (e1 in dnr mode ) 00h 00h 00h
rev. a adv7304a/adv7305a ?27? subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0r egister setting reset 64h sd dnr 1 dnr threshold 0000000 0000011 11111062 11111163 border area 0 2 pixels 14 pixels block size control 08 pixels 1 16 pixels 001 filter a 010 filter b 011 filter c 100 filter d 0d nr mode 1 dnr sharpness mode 0000 0 pixel offset 0001 1 pixel offset 1110 14 pixel offset 1111 15 pixel offset 66h sd gamma a sd gamma curve a data points xxxxxxxxa0 00h 67h sd gamma a sd gamma curve a data points xxxxxxxxa1 00h 68h sd gamma a sd gamma curve a data points xxxxxxxxa2 00h 69h sd gamma a sd gamma curve a data points xxxxxxxxa3 00h 6ah sd gamma a sd gamma curve a data points xxxxxxxxa4 00h 6bh sd gamma a sd gamma curve a data points xxxxxxxxa5 00h 6ch sd gamma a sd gamma curve a data points xxxxxxxxa6 00h 6dh sd gamma a sd gamma curve a data points xxxxxxxxa7 00h 6eh sd gamma a sd gamma curve a data points xxxxxxxxa8 00h 6fh sd gamma a sd gamma curve a data points xxxxxxxxa9 00h 70h sd gamma b sd gamma curve b data points xxxxxxxxb0 00h 71h sd gamma b sd gamma curve b data points xxxxxxxxb1 00h 72h sd gamma b sd gamma curve b data points xxxxxxxxb2 00h 73h sd gamma b sd gamma curve b data points xxxxxxxxb3 00h 74h sd gamma b sd gamma curve b data points xxxxxxxxb4 00h 75h sd gamma b sd gamma curve b data points xxxxxxxxb5 00h 76h sd gamma b sd gamma curve b data points xxxxxxxxb6 00h 77h sd gamma b sd gamma curve b data points xxxxxxxxb7 00h 78h sd gamma b sd gamma curve b data points xxxxxxxxb8 00h 79h sd gamma b sd gamma curve b data points xxxxxxxxb9 00h 7ah sd brightness detect sd brightness value xxxxxxxx read-only 7bh field count register field count xxx read-only reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. reserved code x x read-only dnr block offset sd dnr 2 65h 00h 00h dnr input select dnr mode table viii. sd registers (continued)
rev. a adv7304a/adv7305a ?28? table viii. sd registers (continued) subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 7ch reset register timing reset 0 no reset of timing generator in subcarrier reset mode. 44h, bits 1 and 2 must be set to subcarrier reset. 1 reset timing generator in subcarrier reset mode reserved 0 zero must be written to this bit. r eserve d0 z ero must b e wr i tten to this bit. r eserve d0 z ero must b e wr i tten to this bit. reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. reserved 0 zero must be written to this bit. 00h * line 23 line 313 line 314 line 1 t b hsync vsync t a t c figure 19. timing register 1 in pal mode table ix. macrovision registers * subaddress register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset 7dh reserved 7eh reserved 7fh reserved 80h macrovision mv control bits xxxxxxxxmv 3a [7:0] 00h 81h macrovision mv control bits xxxxxxxxmv 3b [15:8] 00h 82h macrovision mv control bits xxxxxxxxmv 3c [23:16] 00h 83h macrovision mv control bits xxxxxxxxmv 3d [31:24] 00h 84h macrovision mv control bits xxxxxxxxmv 3e [39:32] 00h 85h macrovision mv control bits xxxxxxxxmv 3f [47:40] 00h 86h macrovision mv control bits xxxxxxxxmv 40 [55:48] 00h 87h macrovision mv control bits xxxxxxxxmv 41 [63:56] 00h 88h macrovision mv control bits xxxxxxxxmv 42 [71:64] 00h 89h macrovision mv control bits xxxxxxxxmv 43 [79:72] 00h 8ah macrovision mv control bits xxxxxxxxmv 44 [87:80] 00h 8bh macrovision mv control bits xxxxxxxxmv 45 [95:88] 00h 8ch macrovision mv control bits xxxxxxxxmv 46 [103:96] 00h 8dh macrovision mv control bits xxxxxxxxmv 47 [111:104] 00h 8eh macrovision mv control bits xxxxxxxxmv 48 [119:112] 00h 8fh macrovision mv control bits xxxxxxxxmv 49 [127:120] 00h 90h macrovision mv control bits xxxxxxxxmv 4a [135:128] 00h x mv 4b [136] 0000000 zero must be written to these bits. mv control bit macrovision 91h 00h * macrovision registers are only available on the adv7304a.
rev. a adv7304a/adv7305a ?29? input and output configuration standard definition only the 8- or 10-bit multiplexed input data is input on pins s9es0, with s0 being the lsb in 10-bit input mode. for 8-bit input mode, the data is input on pins s9es2. itu-r.bt601/itu- r.bt656 input standards are supported. in 16-bit input mode, the y pixel data is input on pins s9es2 and crcb data on pins y9ey2. in 20-bit input mode, the y pixel data is input on s9es0 and crcb pixel data on pins y9ey0. the 27 mhz clock input must be input on pin clkin_a. input sync signals are optional and are input on the s_vsync s_hsync s_blank pe ecer s_vsync s_hsync s_blank clkn_a ss h ycc ava ava s prressve scan nly r htv nly ycc p s htv h ycc y p yy cc p cc y p yy c p cc c p ss ycc spte trbt spte spte btat a t rb ps htv h rb p yy r ss b p cc t p clkn_a s p p_vsync p_hsync p_blank pe ecer p_vsync p_hsync p_blank clkn_a ss c cc yy nterlace t prressve ycc c y h ava ava p s sltanes stanar entn an prressve scan r htv ycc ps htv h y p yy cc cc ps p yy p t h r a ycc spte trbt spte spte btat a t t trbttrbt s p ss s lsb p ss t s clkn_a h clkn_b s s p s_vsync s_hsync s_blank h p p_vsync p_hsync p_blank pe ecer s_vsync s_hsync s_blank clkn_a cc cc yy nterlace t prressve ycc y p_vsync p_hsync p_blank clkn_b h ss h ava ava s p s s s_vsync s_hsync s_blank clkn_a p_vsync p_hsync p_blank clkn_b stv ecer h ycc htv ecer cc y h adv7304a/ adv7305a s9es2 c9ec2 y9ey2 figure 23. simultaneous hdtv and sd input if in simultaneous input mode the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the clock align bit must be set accordingly. this also applies if the pixel align b it is set. if the application uses the same clock source for both sd and ps, the c lock align bi t must be set since the phase difference between both inputs is less than 9.25 ns. t delay 9.25ns or t delay 27.75ns figure 24. clock phase with two input clocks
rev. a adv7304a/adv7305a ?30? progressive scan at 27 mhz or 54 mhz ycrcb progressive scan data can be input at 27 mhz or 54 mhz. the input data is interleaved onto a single 10-bit bus and is input on pins y9ey0. for ps input only mode, the input clock must be input on clkin_a. in simultaneous sd/hd mode, the input clock is input on clkin_b. mpeg2 decoder p_vsync p_hsync p_blank clkin_a y9ey0 interlaced to progressive ycrcb 10 3 adv7304a/ adv7305a 27mhz or 54mhz ycrcb figure 25. 1 10-bit ps @ 27 mhz or 54 mhz when the input sequence of the ps data, i.e., 10-bit interleaved at 27 mhz, starts with y0 data, as shown in figure 26, pixel align [subaddress 01h] must be set to 0. in this case, the timing information embedded in the data stream is recognized and the video data is transferred to the according y channel and crcb channel processing blocks. pixel input data 3ff 00 00 xy y0 cb0 y1 cr0 clkin_a figure 26. input sequence in ps 10-bit interleaved mode, eav/sav followed by y0 data if the input sequence starts with cb0 data as shown in figure 27, initially pixel align [subaddress 01h] must be set to 0. this ensures that the adv7304a/adv7305a locks to the input sequence in decoding the embedded timing information correctly. for correct color decoding, the pixel align bit [subaddress 01h] must then be set to l after a delay of one field. the adv7304a/adv7305a is now in free run mode, any changes in the timing information are ignored. pixel input data 3ff 00 00 xy cb0 y0 cr0 y1 clkin_a figure 27. input sequence in ps 10-bit interleaved mode, eav/sav followed by cb0 data ps 10-bit interleaved at 54 mhz must be input with separate timing signals. eav/sav codes cannot be used in this mode.
rev. a adv7304a/adv7305a ?31? table x. overview of all possible input configurations input format total bits input video input pins subaddress r egister setting itu-r.bt656 8 4:2:2 ycrcb s9es2 [msb = s9] 01h, 48h 00h, 00h 10 4:2:2 ycrcb s9es0 [msb = s9] 01h, 48h 00h, 10h y s9es2 [msb = s9] cr cb y9ey2 [msb = y9] y s9es0 [msb = s9] cr cb y9ey0 [msb = y9] ps only 8 (27 mhz clock) 4:2:2 ycrcb y9ey2 [ msb = y9] 01h, 13h 10h, 40h 10 (27 mhz clock) 4:2:2 ycrcb y9ey0 [ msb = y9] 01h, 13h 10h, 44h 8 (54 mhz clock) 4:2:2 ycrcb y9ey2 [ msb = y9] 01h, 13h 70h, 40h 10 (54 mhz clock) 4:2:2 ycrcb y9ey0 [ msb = y9] 01h, 13h 10h, 44h y y9ey2 [msb = y9] cr cb c9ec2 [msb = c9] y y9ey0 [msb = y9] cr cb c9ec0 [msb = c9] y y9ey2 [msb = y9] cb c9ec2 [msb = c9] cr s9es2 [msb = s9] y y9ey0 [msb = y9] cb c9ec0 [msb= c9] cr s9es0 [msb = s9] hdtv only 8 4:2:2 ycrcb y9ey2 [ msb = y9] 01h, 13h 20h, 40h 10 4:2:2 ycrcb y9ey0 [ msb = y9] 01h, 13h 20h, 44h y y9ey2 [msb = y9] crcb c9ey2 [msb = c9] y y9ey0 [msb = y9] cr cb c9ec0 [msb = c9] y y9ey2 [msb = y9] cb c9ey2 [msb = c9] cr s9es2 [msb = s9] y y9ey0 [msb = y9] cb c9ec0 [msb = c9] cr s9es0 [msb = s9] hd rgb gy 9ey2 [msb = y9] b c9ec2 [msb = c9] r s9es2 [msb = s9] g y9ey0 [msb = y9] b c9ec0 [msb = c9] r s9es0 [msb = s9] sd 8 4:2:2 ycrcb s9es2 [msb = s9] 01h 40h 13h 40h 48h 00h sd 10 4:2:2 ycrcb s9es0 [msb = s9] 01h 40h 13h 44h 48h 10h sd 8 4:2:2 ycrcb s9es2 [msb = s9] 01h 30h, 50h, or 60h 4:2:2 y y9ey2 [ msb = y9] 13h 40h cr cb c9ec2 [msb = c9] 48h 00h sd 10 4:2:2 ycrcb s9es0 [msb = s9] 01h 30h, 50h, or 60h 4:2:2 y y9ey0 [ msb = y9] 13h 44h cr cb c9ec0 [msb = c9] 48h 10h y9ey0 [msb = y9] hd 16 hd 20 itu-r.bt656 and ps or hdtv itu-r.bt656 and ps ps 10 4:2:2 ycrcb ps 8 4:2:2 ycrcb y9ey2 [msb = y9] 01h, 13h 20h, 00h 01h, 13h 20h, 04h 01h, 13h, 15h 10h or 20h, 00h, 02h 01h, 13h, 15h 10h or 20h, 04h, 02h 01h, 13h 20h, 40h 01h, 13h 20h, 44h 01h, 13h 10h, 00h 01h, 13h 10h, 04h 01h, 13h 10h, 40h 01h, 13h 10h, 44h 01 h, 48h 00h, 18h 01 h, 4 8h 00h, 08h 30 4:4:4 24 30 4:4:4 4:4:4 16 24 4:4:4 4:2:2 20 4:2:2 20 4:2:2 4:2:2 16 24 30 4:4:4 4:4:4 4:2:2 4:2:2 16 20
rev. a adv7304a/adv7305a ?32? output configuration tables xiexiii demonstrate what output signals are assigned to the dacs when corresponding control bits are set. table xi. output configuration in sd only mode rgb/yuv o/p sd dac o/p 1 sd dac o/p 2 addr 02h, bit 5 addr 42h, bit 2 addr 42h, bit 1 dac a dac b dac c dac d dac e dac f 00 0 cvbs luma chroma g b r 00 1g br cvbs luma chroma 01 0g luma chroma cvbs b r 01 1 cvbs b r g luma chroma 10 0 cvbs luma chroma y u v 10 1y uv cvbs luma chroma 11 0y luma chroma cvbs u v 11 1 cvbs u v y luma chroma table xii. output configuration in hd only mode hd i/p hd rgb i/p rgb/yuv o/p hd color swap format addr 15h, bit 1 addr 02h, bit 5 addr 15h, bit 3 dac a dac b dac c dac d dac e dac f ycrcb 4:2:2 n/a 0 0 n/a n/a n/a g b r ycrcb 4:2:2 n/a 0 1 n/a n/a n/a g r b ycrcb 4:2:2 n/a 1 0 n/a n/a n/a y pb pr ycrcb 4:2:2 n/a 1 1 n/a n/a n/a y pr pb ycrcb 4:4:4 n/a 0 0 n/a n/a n/a g b r ycrcb 4:4:4 n/a 0 1 n/a n/a n/a g r b ycrcb 4:4:4 n/a 1 0 n/a n/a n/a y pb pr ycrcb 4:4:4 n/a 1 1 n/a n/a n/a y pr pb rgb 4:4:4 100n/a n/a n/a g b r rgb 4:4:4 101n/a n/a n/a g r b rgb 4:4:4 110n/a n/a n/a g b r rgb 4:4:4 111n/a n/a n/a g r b table xiii. output configuration in simultaneous sd/hd mode rgb/yuv o/p hd color swap input formats addr 02h, bit 5 addr 15h, bit 3 dac a dac b dac c dac d dac e dac f sd ycrcb in 4:2:2 and hd ycrcb in 4:2:2 0 0 cvbs luma chroma g b r sd ycrcb in 4:2:2 and hd ycrcb in 4:2:2 0 1 cvbs luma chroma g r b sd ycrcb in 4:2:2 and hd ycrcb in 4:2:2 1 0 cvbs luma chroma y pb pr sd ycrcb in 4:2:2 and hd ycrcb in 4:2:2 1 1 cvbs luma chroma y pr pb
rev. a adv7304a/adv7305a ?33? timing modes hd async timing mode [subaddress 10h, bits 3e2] for any input data that does not conform to smpte293m, smpte274m, smpte296m, or itu-r.bt1358 standards, an asynchronous timing mode can be used to interface to the adv7304a/adv7305a. timing control signals for hsync, vsync, and blank have to be programmed by the user. macrovision is not available in async timing mode. figure 28 shows an example of how to program the adv7304a/ adv7305a to accept a different high definition standard other than smpte293m, smpte274m, smpte296m, or itu-r.bt1358 standards. table xiv must be followed when programming the control sig- nals in async timing mode. hd timing reset a timing reset is achieved in setting the hd timing reset con- trol bit at address 14h from 0 to 1. in this state, the horizontal and vertical counters will remain reset. on setting this bit back to 0, the internal counters will again commence counting. the minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. this timing reset applies to the hd timing counters only. sd timing realtime control, subcarrier reset, timing reset [subaddress 44h, bits 2e1] together with the rtc_scr_tr pin and sd mode register 3 [address 44h, bits 1e2], the adv7304a/adv7305a can be used in timing reset mode, subcarrier phase reset mode, or rtc mode. a. a timing reset is achieved in a low-to-high transition on the rtc_scr_tr pin (pin 31). in this state, the horizontal and vertical counters will remain reset. on releasing this pin (set to low), the internal counters will again commence counting. the minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. this timing reset applies to the sd timing counters only. b. subcarrier phase reset, a low-to-high transition on the rtc_scr_tr pin (pin 31), will reset the subcarrier phase to zero when the sd rtc/tr/scr control bits at address 44h are set to 01. this reset signal will have to be held high for a minimum of one clock cycle. since the field counter is not reset, it is recommended to apply the reset in field 7 (pal). the reset of the phase will then occur on the next field by being correctly lined up with the internal counters. the field count r egister at address 7bh can be used to identify the number of the active field. c. in rtc mode, the adv7304a/adv7305a can be used to lock to an external video source. the realtime control mode allows the adv7304a/adv7305a to automatically alter the subcarrier frequency to compensate for line length variations. when the part is connected to a device that outputs a digital data stream in the rtc format (such as a adv7185 video decoder, see figure 29), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. this digital data stream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. 00h should be written into all four subcarrier frequency registers when using this mode. clk active video programmable input timing analog output ab c d 81 66 66 243 1920 horizontal sync e p_hsync p_vsync p_blank * * set address 10h, bit 6 to 1 figure 28. async timing mode, programming input control signals for smpte295m compatibility
rev. a adv7304a/adv7305a ?34? table xiv. truth table p_hsync p_vsync p_blank = = = reset p t avaava reset reset tal tn tal tn snals sppresse val ve tn actve ac pel ata val reset ts
rev. a adv7304a/adv7305a C35C vertical blanking interval the adv7304a/adv7305a accepts input data that contains vbi data (cgms, wss, vits, and so on) in sd and hd modes. for smpte293m (525 p) standards, vbi data can be inserted on l ines 13 to 42 of each frame, or lines 6 to 43 for itu-r.bt1358 ( 625 p) standard. for sd ntsc, this data can be present on lines 10 to 20; in pal, on lines 7 to 22. if vbi is disabled [address 11h, bit 4 for hd; address 43h, bit 4 for sd], vbi data is not present at the output and the entire vbi is blanked. these control bits are valid in all master and slave modes. in slave mode 0, if vbi is enabled, the blanking bit in the eav/sav code is overwritten and it is possible to use vbi in this timing mode as well. in slave mode 1 or 2, the blank control bit must be set to enabled [address 4ah, bit 3] to allow vbi data to pass through the adv7304a/adv7305a. otherwise, the adv7304a/ adv7305a automatically blanks the vbi to standard. if cgms is enabled and vbi disabled, the cgms data will nevertheless be available at the output. sd subcarrier frequency registers [subaddress 4ch?fh] four 8-bit wide registers are used to set up the subcarrier fre- quency. the value of these registers is calculated in using the equation: subcarrier frequency register = # # of subcarrier frequency cycles in one video line of mhz clock cycles in one video line 27 2 32 example: ntsc mode subcarrier frequency = 227 5 1716 2 569408542 32 . = * subcarrier register value = 21f07c1eh sd f sc register 0: 1eh sd f sc register 1: 7ch sd f sc register 2: f0h sd f sc register 3: 21h refer to the mpu port description section for more detail on how to access the subcarrier frequency registers. subcarrier phase register [subaddress 50h, 5ch, bits 7, 6] ten bits are used to set up the subcarrier phase. each bit repre- sents 0.352 . for normal operation, this register is set to 00h. filters table xv shows an overview of the programmable filters avail- able on the adv7304a/adv7305a. table xv. selectable filters filter subaddress sd luma lpf ntsc 40h sd luma lpf pal 40h sd luma notch ntsc 40h sd luma notch pal 40h sd luma ssaf 40h sd luma cif 40h sd luma qcif 40h sd chroma 0.65 mhz 40h sd chroma 1.0 mhz 40h sd chroma 1.3 mhz 40h sd chroma 2.0 mhz 40h sd chroma 3.0 mhz 40h sd chroma cif 40h sd chroma qcif 40h sd uv ssaf 42h hd chroma input 13h hd sync filter 13h hd chroma ssaf 13h hd sync filter frequency ?mhz 0.5 ?.5 030 5 gain ?db 10 15 20 25 0.4 0.1 ?.2 ?.3 ?.4 0.3 0.2 0 ?.1 figure 31. hd sync filter enabled frequency ?mhz 0.5 ?.5 030 5 gain ?db 10 15 20 25 0.4 0.1 ?.2 ?.3 ?.4 0.3 0.2 0 ?.1 figure 32. hd sync filter disabled * rounded to the nearest integer
rev. a adv7304a/adv7305a ?36? hd 4:2:2 to 4:4:4 interpolation filters and chroma ssaf it is recommended to input data in 4:2:2 input mode to make use of the hd chroma ssafs on the adv7304a/adv7305a. this filter has a 0 db pass-band response and prevents signal components from being folded back into the frequency band. in 4:4:4 input mode, the video data is already interpolated by the external input device and the chroma ssafs of the adv7304a/ adv7305a are bypassed. the chroma ssaf is controlled with address 13h, bit 5. when the hd input format is 4:2:2, the hd chroma input bit [address 13h, bit 6] must be set to 1. 2 /4 /8 oversampling filters the oversampling filters are enabled in setting the pll on control [subaddress 00h, bit 1] to 1. if enabled, ps and itu-r.bt656 data is output at a rate of 108 mhz, hdtv at a rate of 148 mhz. frequency e mhz 0 e50 e80 0 110 10 gain e db 20 30 40 50 60 70 80 90 100 e10 e40 e60 e70 e20 e30 figure 33. y ? ps 4 oversampling filter frequency e mhz 1.0 e1.5 e3.0 02 gain e db 46810 12 14 0.5 e1.0 e2.0 e2.5 0 e0.5 figure 34. y ? ps 4 oversampling filter in the pass band frequency e mhz 0 e50 e80 0 160 20 gain e db 40 60 80 100 120 140 e10 e40 e60 e70 e20 e30 figure 35. y ? hdtv 2 oversampling filter frequency e mhz 1.0 e1.5 e3.0 05 gain e db 10 15 20 25 30 35 0.5 e1.0 e2.0 e2.5 0 e0.5 figure 36. y ? hdtv 2 oversampling filter in the pass band
rev. a adv7304a/adv7305a ?37? frequency e mhz 0 e50 e80 0 110 10 gain e db 20 30 40 50 60 70 80 90 100 e10 e40 e60 e70 e20 e30 figure 37. uv ? hdtv 2 oversampling filter frequency e mhz 0 e50 e80 0 110 10 gain e db 20 30 40 50 60 70 80 90 100 e10 e40 e60 e70 e20 e30 figure 38. uv ? ps 4 oversampling filter, linear frequency e mhz 1.0 e1.5 e3.0 018 2 gain e db 46810 12 14 16 0.5 e1.0 e2.0 e2.5 0 e0.5 figure 39. uv ? hdtv 2 oversampling filter, pass band frequency e mhz 0 e50 e80 0 110 10 gain e db 20 30 40 50 60 70 80 90 100 e10 e40 e60 e70 e20 e30 figure 40. uv ? ps 4 oversampling filter, ssaf
rev. a adv7304a/adv7305a C38C sd internal filter response [subaddress 42h, bit 0] the y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost/attenua- tion, a cif response, and a qcif response. the uv filter supports several different frequency responses, including six low-pass responses, a cif response, and a qcif response, as can be seen in figures 41 C 59. if sd ssaf gain is enabled, there is the option of 12 responses in the range from C 4d b to +4 db. the desired response can be chosen by the user by programming the correct value via the i 2 c. the variation of frequency responses can be seen in figures 41 C 59. in addition to the chroma filters listed above, the adv7304a/ adv7305a contains an ssaf filter specifically designed for and applicable to the color difference component outputs u and v. this filter has a cutoff frequency of approximately 2.7 mhz and C 40 db at 3.8 mhz, as shown in figure 41. this filter can be controlled via address 42h, bit 0. if this filter is disabled, the selectable chroma filters shown in table xvi can be used for the cvbs or chroma signal. table xvi. internal filter specifications pass-band 3 db filter ripple 1 (db ) bandwidth 2 (mhz) luma lpf ntsc 0.16 4.24 luma lpf pal 0.1 4.81 luma notch ntsc 0.09 2.3/4.9/6.6 luma notch pal 0.1 3.1/5.6/6.4 luma ssaf 0.04 6.45 luma cif 0.127 3.02 luma qcif monotonic 1.5 chroma 0.65 mhz monotonic 0.65 chroma 1.0 mhz monotonic 1 chroma 1.3 mhz 0.09 1.395 chroma 2.0 mhz 0.048 2.2 chroma 3.0 mhz monotonic 3.2 chroma cif monotonic 0.65 chroma qcif monotonic 0.5 notes 1 pass-band ripple is the maximum fluctuations from the 0 db response in the pass band, measured in db. the pass band is defined to have 0 hz to fc (hz) frequency limits for a low-pass filter, 0 hz to f1 (hz) and f2 (hz) to infinity for a notch filter, where fc, f1, f2 are the C 3 db points. 2 +3 db bandwidth refers to the C 3 db cutoff frequency. frequency ?mhz 0 02345 gain ?db ?0 ?0 ?0 ?0 ?0 ?0 6 1 figure 41. uv ssaf filter frequency ?mhz 0 02468 12 magnitude ?db ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 figure 42. luma ntsc low-pass filter frequency ?mhz 0 02468 12 magnitude ?db ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 figure 43. luma pal low-pass filter
rev. a adv7304a/adv7305a ?39? frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 44. luma ntsc notch filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 45. luma pal notch filter frequency e mhz 0 e50 e80 0 110 10 gain e db 20 30 40 50 60 70 80 90 100 e10 e40 e60 e70 e20 e30 figure 46. luma ssaf filter up to 108 mhz frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 47. luma ssaf filter up to 12 mhz frequency e mhz 4 01234 7 magnitude e db 2 e2 e6 e8 e12 0 e4 5 e10 6 figure 48. luma ssaf filter, programmable responses frequency e mhz 01234 7 magnitude e db 5 4 2 1 e1 3 5 0 6 figure 49. luma ssaf filter, programmable gain
rev. a adv7304a/adv7305a ?40? frequency e mhz 01234 7 magnitude e db 1 0 e2 e3 e5 e1 5 e4 6 figure 50. luma ssaf filter, programmable attenuation frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 51. luma cif lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 52. luma qcif lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 53. chroma 3.0 mhz lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 54. chroma 2.0 mhz lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 55. chroma 1.3 mhz lp filter
rev. a adv7304a/adv7305a ?41? frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 56. chroma 1.0 mhz lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 57. chroma 0.65 mhz lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 58. chroma cif lp filter frequency e mhz 0 02468 12 magnitude e db e10 e30 e50 e60 e70 e20 e40 10 figure 59. chroma qcif lp filter
rev. a adv7304a/adv7305a ?42? color controls and rgb matrix hd y color, hd cr color, hd cb color [subaddresses 16he18h] three 8-bit wide registers at addresses 16h, 17h, and 18h are used to program the output color of the internal hd test pattern genera- tor, be it the lines of the crosshatch pattern or the uniform field test pattern. they are not functional as color controls on external pixel data input. for this purpose, the rgb matrix is used. the standard used for the values for y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the itu-r.bt601e itu-r.bt604 standards. table xvii shows sample color values to be programmed into the color registers when output standard selection is set to eia 770.2. table xvii. sample color values for eia 770.2 output standard selection sample color y color cr color cb color value value value white 235 (eb) 128 (80) 128 (80) black 16 (10) 128 (80) 128 (80) red 81 (51) 240 (f0) 90 (5a) green 145 (91) 34 (22) 54 (36) blue 41 (29) 110 (6e) 240 (f0) yellow 210 (d2) 146 (92) 16 (10) cyan 170 (aa) 16 (10) 166 (a6) magenta 106 (6a) 222 (de) 202 (ca) hd rgb matrix [subaddresses 03he09h] when the programmable rgb matrix is disabled [address 02h, bit 3], the internal rgb matrix takes care of all ycrcb to yuv or rgb scaling according to the input standard programmed into the device. when the programmable rgb matrix is enabled, the color components are converted according to the smpte274m standard (1080 i): yrg b cb b y ry '. ' . '. ' ' . . '' ' . . '' = () + () + () = ? ? () = ? ? () cr this is reflected in the preprogrammed values for gy = 13bh, rv = 1f0h, bu = 248h, gv = 93h, and gu = 3bh. if another input standard is used, the scale values for gy, gu, gv, bu, and rv have to be adjusted according to this input standard. it must be considered by the user that the color com- ponent conversion might use different scale values. for example, smpte293m uses the following conversion: yr g b cb b y ry '. ' . '. ' ' . . '' ' . . '' = () + () + () = ? ? () = ? ? () cr the programmable rgb matrix can be used to control the hd output levels in cases where the video output does not conform to standards due to altering the dac output stages, such as ter- mi nation resistors. the programmable rgb matrix is used for external hd data and is not functional when the hd test pattern is enabled. to make use of the programmable rgb matrix, the ycrcb data should contain the hsync signal on the y channel only. the rgb matrix should be enabled [address 02h, bit 3], the output should be set to rgb [address 02h, bit 3], sync on prpb should be disabled [address 15h, bit 2], and sync on rgb is optional [address 02h, bit 4]. gy at addresses 03h and 05h control the output levels on the green signal, bu at 04h and 08h the blue signal output levels, and rv at 04h and 09h the red output levels. to control yprpb output levels, yuv output should be enabled [address 02h, bit 5]. in this case, gy [address 05h; address 03, bits 0?] is used for the y output, rv [address 09; address 04, bits 0?] is used for the pr output, and bu [address 08h; address 04h, bits 2?] is used for the pb output. if rgb output is selected, the rgb matrix scaler uses the fol- lowing equations: rgyyrv ggyygu cb gv =+ =? ? cr cr b=gy y+ bu cb if yuv output is selected, the following equations are used: rrv ggyy bbucb = = = cr on power-up, the rgb matrix is programmed with default values: address 03h: 03h address 04h: f0h address 05h: 4eh address 06h: 0eh address 07h: 24h address 08h: 92h address 09h: 7ch when the programmable rgb matrix is not functional, the adv7304a/adv7305a automatically scales ycrcb inputs to all standards supported. for smpte293m, the register values are as follows: address 03h: 03h address 04h: 1eh address 05h: 4eh address 06h: 1bh address 07h: 38h address 08h: 8bh address 09h: 6eh address 15h, bit 3 must be set to ??in this mode. sd color control [subaddresses 5ch, 5dh, 5eh, and 5fh] sd y scale, sd cr scale, and sd cb scale are three 10-bit wide control registers to scale the y, u, and v output levels. each of these registers represents the value required to scale the u or v level from 0 to 2.0 and the y level from 0 to 1.5 of its initial level. the value of these 10 bits is calculated using the equation: y, u, or v scalar value = scale factor 512
rev. a adv7304a/adv7305a ?43? example: scale factor = 1.18 y, u, or v scale value = 1.18 512 = 665.6 y, u, or v scale value = 665 (rounded to nearest integer) y, u, or v scale value = 1010011001 b address 5ch, sd lsb register = 15h address 5dh, sd y scale register = a6h address 5eh, sd v scale register = a6h address 5fh, sd u scale register = a6h sd hue adjust value [subaddress 60h] t he hue adjust value is used to adjust the hue on the compos- ite and chroma outputs. these eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. the adv7304a/adv7305a provides a range of ( ) () ( hcr ?128) example: to adjust the hue by +4 + +== 4 0 17578125 128 151 97 . h where 151 is rounded to the nearest integer. to adjust the hue by e4 +== + + sd brightness value (hex) = ( ire value 2.015631) 28h = (20 2.015631) = 40.31262 standard: pal. to add e7 ire brightness level, write 72h to address 61h, sd brightness: sd brightness value (hex) = ( ire value 2.015631) 0001110 b = (7 2.015631) = 14.109417 0001110 in twos complement equals 1110010, or 72h. sd brightness detect [subaddress 7ah] the adv7304a/adv7305a allows monitoring of the bright- ness level of the incoming video data. the brightness detect register is a read-only register. double buffering [subaddress 13h, bit 7; subaddress 48h, bit 2] double buffered registers are updated once per field on the falling edge of the vsync signal. double buffering improves the overall performance since modifications to register settings will not be made during active video but take effect on the start of the active video. double buffering can be activated on the following hd regis- ters: hd gamma a and gamma b curves, and hd cgms registers. double buffering can be activated on the following sd registers: sd gamma a and gamma b curves, sd y scale, sd u scale, sd v scale, sd brightness, sd closed captioning, and sd macrovision bits 5e0. table xviii. brightness control values setup level? setup level? setup level? sd brightness ntsc w/pedestal (ire) ntsc w/o pedestal (ire) pal (ire) value 22.5 +15 +15 1eh 15 +7.5 +7.5 0fh 7.5 0 0 00h 0 e7.5 e7.5 71h values in the range from 3fh to 44h might result in an invalid output signal. ntsc without pedestal no setup value added positive setup value added 100 ire 0 ire negative setup value added e7.5 ire +7.5 ire figure 60. examples for brightness control values
rev. a adv7304a/adv7305a ?44? gamma correction [subaddresses 21he37h for hd; subaddresses 66he79h for sd] gamma correction is available for sd and hd video. for each standard there are 20 8-bit wide registers. they are used to program the gamma correction curves a and b. hd gamma curve a is programmed at addresses 24he2dh and hd gamma curve b at 2ehe37h. sd gamma curve a is pro- grammed at addresses 66he6fh, and sd gamma curve b at addresses 70he79h. generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied wher- ever nonlinear processing is used. gamma correction uses the function: signal signal out in = () equals the gamma power factor. gamma correction is performed on the luma data only. the user has the choice to use two different curves, curve a or curve b. at any one time only one of these curves can be used. the response of the curve is programmed at 10 predefined locations. in changing the values at these locations, the gamma curve can be modified. between these points, linear interpola- tion is used to generate intermediate values. considering the curve to have a total length of 256 points, the 10 locations are: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. locations 0, 16, 240, and 255 are fixed and cannot be changed. for the length of 16 to 240, the gamma correction curve must be calculated as: yx = y = gamma corrected output, x = linear input signal, and = the gamma power factor. to program the gamma correction registers, the values for y must be calculated using the formula: y x n n = ? ? ? ? ? ? ? ? () + ? () x (n?6) = the value for x along the x-axis at points n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224; y n = the value for y along the y-axis, which has to be written into the gamma cor- rection register. example: y y y y 24 05 32 05 48 05 64 05 8 224 224 16 58 16 224 224 16 76 32 224 224 16 101 48 224 224 16 120 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += y y y y 80 05 96 05 128 05 160 05 64 224 224 16 136 80 224 224 16 150 112 224 224 16 174 144 224 224 16 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = = = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += = ? ? ? ? ? ? ? ? ? ? ? ? ? ? += y y . . the gamma curves shown in figures 61 and 62 are examples. any user defined curve is acceptable in the range of 16?40. location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.5 signal input signal output gamma corrected amplitude figure 61. signal input (ramp) and signal output for gamma 0.5 * rounded to the nearest integer
rev. a adv7304a/adv7305a ?45? location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.3 0.5 1.5 1.8 signal input gamma corrected amplitude figure 62. signal input (ramp) and selectable gamma output hd sharpness filter control and adaptive filter control [subaddresses 20h and 38he3dh] there are three filter modes available on the adv7304a/ adv7305a: sharpness filter mode and two adaptive filter modes. hd sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in figure 63, the following register settings must be used: hd sharpness filter must be enabled and hd adaptive filter enable must be set to disabled. to select one of the 256 individual responses, the correspond- ing gain values for each filter, which range from e8 to +7, must be programmed into the hd sharpness filter gain register at address 20h. hd adaptive filter mode the hd adaptive filter threshold a, b, and c registers, the hd adaptive filter gain 1, 2, and 3 registers, and the hd sharpness filter gain register are used in adaptive filter mode. to activate the adaptive filter control, the hd sharpness filter and hd adaptive filter enable must be enabled. the derivative of the incoming signal is compared to the three programmable threshold values: hd adaptive filter threshold a, b, and c. the recommended threshold range is from 16e 235, although any value in the range of 0e255 can be used. the edges can then be attenuated with the settings in hd adaptive filter gain 1, 2, and 3 re gisters and hd s harpness filter gain register. according to the settings of the hd adaptive filter mode con- trol, there are two adaptive filter modes available: 1. mode a is used when adaptive filter mode is set to 0. in this case, filter b (lpf) will be used in the adaptive filter block. also, only the programmed values for gain b in the hd sharpness filter gain, hd adaptive filter gain 1, 2, and 3 are applied when needed. the gain a values are fixed and cannot be changed. 2. mode b is used when adaptive filter mode is set to 1. in this mode, a cascade of filter a and filter b is used. both settings for gain a and gain b in the hd sharpness filter gain, hd adaptive filter gain 1, 2, and 3 become active when needed. frequency e mhz magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 filter a response e gain ka frequency e mhz magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 filter b response e gain kb frequency e mhz magnitude e linear scale 1.0 1.1 1.2 1.3 1.4 1.5 1.6 024681012 input signal: step frequency response in sharpness filter mode with ka = 3 and kb = 7 figure 63. sharpness and adaptive filter control block
rev. a adv7304a/adv7305a ?46? hd sharpness filter and adaptive filter application examples hd sharpness filter application the hd sharpness filter can be used to enhance or attenuate the y video output signal. the register settings in tables xix and xx are used to achieve the results shown in figure 64. input data was generated by an external signal source. table xix. sharpness filter on frequency sweep address register setting reference * 00h fch 01h 10h 02h 20h 10h 00h 11h 81h 20h 00h a 20h 08h b 20h 04h c 20h 40h d 20h 80h e 20h 22h f * see figure 64. the effect of the sharpness filter can also be seen when using the internally generated crosshatch pattern. table xx. sharpness filter on internal test pattern address register setting 00h fch 01h 10h 02h 20h 10h 00h 11h 85h 20h 99h in toggling the sharpness filter enable bit [address 11h, bit 8], it can be seen that the line contours of the crosshatch pattern change their sharpness. adaptive filter control application figure 65 shows a typical signal to be processed by the adaptive filter control block. : 692mv @: 446mv : 332ns @: 12.8ms figure 65. input signal to adaptive filter control : 690mv @: 446mv : 332ns @: 12.8ms figure 66. output signal after adaptive filter control the register settings in table xxi are used to obtain the results shown in figure 66, i.e., to remove the ringing on the y signal. input data was generated by an external signal source. f e d a b c figure 64. hd sharpness filter control with different gain settings for hd sharpness filter gain value
rev. a adv7304a/adv7305a ?47? table xxi. adaptive filter control on step input signal address register setting 00h fch 01h 38h 02h 20h 10h 00h 11h 81h 15h 80h 20h 00h 38h ach 39h 9ah 3ah 88h 3bh 28h 3ch 3fh 3dh 64h all other register settings are 00h. when changing the adaptive filter mode to mode b [address 15h, bit 6], the output in figure 67 can be obtained. : 674mv @: 446mv : 332ns @: 12.8ms figure 67. output signal from adaptive filter control the adaptive filter control can also be demonstrated using the internally generated crosshatch test pattern and toggling the adap- tive filter control bit [address 15h, bit 7], shown in table xxii. table xxii. adaptive filter control on internal test pattern address register setting 00h fch 01h 38h 02h 20h 10h 00h 11h 85h 15h 80h 20h 00h 38h ach 39h 9ah 3ah 88h 3bh 28h 3ch 3fh 3dh 64h sd digital noise reduction [subaddresses 63h, 64h, and 65h] dnr is applied to the y data only. a filter block selects the high frequency, low amplitude components of the incoming signal (dnr input select). the absolute value of the filter output is compared to a programmable threshold value (dnr threshold control). there are two dnr modes available: dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. a programmable amount (coring gain border, coring gain data) of this noise signal will be subtracted from the original signal. in dnr sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. otherwise, if the level exceeds the threshold now being identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) will be added to the origi- nal signal in order to boost high frequency components and to sharpen the video image. in mpeg systems, it is common to process the video information in blocks of 8 8 pixels for mpeg2 systems, or 16 16 pixels for mpeg1 systems (block size control). dnr can be applied to the resulting block transition areas that are known to contain noise. generally, the block transition area contains two pixels. it is possible to define this area to contain four pixels (border area). it is also possible to compensate for variable block positioning or differences in ycrcb pixel timing with the use of the (dnr block offset). block size control border area block offset coring gain data coring gain border gain dnr control filter output > threshold ? input filter block filter output < threshold dnr out main signal path add signal above threshold range from original signal dnr sharpness mode noise signal path y data input block size control border area block offset coring gain data coring gain border gain dnr control filter output < threshold ? input filter block filter output > threshold dnr out main signal path subtract signal in threshold range from original signal dnr mode noise signal path y data input figure 68. dnr block diagram
rev. a adv7304a/adv7305a C48C the digital noise reduction registers are three 8-bit wide registers. they are used to control the dnr processing. coring gain border [address 63h, bits 3?] these four bits are assigned to the gain factor applied to the border areas. in dnr mode, the range of gain values is 0 C 1, in increments of 0.125. this factor is applied to the dnr filter output that lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5, in increments of 0.0625. this factor is applied to the dnr filter output that lies above the threshold range. the result is added to the original signal. coring gain data [address 63h, bits 7?] these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode, the range of gain values is 0 C 1, in increments of 0.125. this factor is applied to the dnr filter output that lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 C 0.5, in increments of 0.0625. this factor is applied to the dnr filter output that lies above the threshold range. the result is added to the original signal. o x x x x x x o o x x x x x x o o x x x x x x o o x x x x x x o o x x x x x x o o x x x x x x o dnr27 ?dnr24 = 01hex offset caused by variations in input timing apply border coring gain apply data coring gain figure 69. dnr block offset control dnr threshold [address 64h, bits 5?] these six bits are used to define the threshold value in the range of 0 to 63. the range is an absolute value. border area [address 64h, bit 6] in setting this bit to a logic 1, the block transition area can be defined to consist of four pixels. if this bit is set to a logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (n tsc) 8 8 pixel block 8 8 pixel block 2 pixel border data figure 70. dnr border area block size control [address 64h, bit 7] this bit is used to select the size of the data blocks to be pro- cessed. setting the block size control function to a logic 1 defines a 16 16 pixel data block, a logic 0 defines an 8 8 pixel data block, where 1 pixel refers to 2 clock cycles at 27 mhz. dnr input select control [address 65h, bits 2?] three bits are assigned to select the filter that is applied to the incoming y data. the signal that lies in the pass band of the selected filter is the signal that will be dnr processed. the figure below shows the filter responses selectable with this control. filter c filter b filter a filter d frequency ?hz 0 012 3 456 0.2 0.4 0.6 0.8 1.0 figure 71. dnr input select dnr mode control [address 65h, bit 3] this bit controls the dnr mode selected. a logic 0 selects dnr mode, and logic 1 selects dnr sharpness mode. dnr works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the origi- nal signal, since this data is assumed to be valid data and not noise. the overall effect is that the signal will be boosted (similar to using extended ssaf filter). block offset control [address 65h, bits 7?] four bits are assigned to this control, which allow s a shift of the data block of 15 pixels maximum. consider the coring gain posi- tions fixed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
rev. a adv7304a/adv7305a C49C sd active video edge [subaddress 42h, bit 7] when the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that maximum transitions on these pixels are not possible. the scaling factors are 1/8 , 1/2 , and 7/8 . all other active video passes through unprocessed. 100 ire 0 ire 100 ire 12.5 ire 87.5 ire 0 ire 50 ire luma channel with acti ve video edge disabled luma channel with acti ve video edge enabled figure 72. active video edge functionality example board design and layout considerations dac termination and layout considerations the adv7304a/adv7305a contain an on-board voltage refer- ence. the v ref pi n is normally terminated to v aa through a 0.1 f capacitor when the internal v ref is used. alternatively, the adv7304a/adv7305a can be used with an external v ref (e.g., ad1580). the r set resistors are connected between the r set pi ns and agnd and are used to control the full-scale output current and, therefore, the dac voltage output levels. for full-scale output, r set must have a value of 760 ? . the r set values should not be changed. r load h as a value of 150 ? for fu ll- scale output. video output buffer and optional output filter output buffering on all six dacs is necessary in order to drive output devices, such as sd or hd monitors. analog devices produces a range of suitable op amps for this application, for example the ad8061. more information on line driver buffering circuits is given in the relevant op amp data sheets. an optional analog reconstruction lpf might be required as an antialias filter if the adv7304a/adv7305a is connected to a de vice that requires this filtering. the filter specifications vary with the application, see table xxiii. table xxiii. external filter requirements input external filter cutoff mode oversampling frequency attenuation sd 2 >6.5 mhz C 50 db @ 20.5 mhz sd 8 >6.5 mhz C 50 db @ 101.5 mhz ps 1 >12.5 mhz C 50 db @ 14.5 mhz ps 4 >12.5 mhz C 50 db @ 95.5 mhz hdtv 1 >30 mhz C 50 db @ 44.25 mhz hdtv 2 >30 mhz C 50 db @ 118.5 mhz 600r 1.8k 300r 47pf 300r dac o/p 75r bnc o/p 6.8 h 6.8 h figure 73. example for output filter for sd, 8 oversampling circuit frequency response ?mhz ?0 110 100 0n ?40 6n ?20 12n 0 18n 120 24n 240 30n 360 36n 480 ?0 ?0 ?0 ?0 ?0 0 group delay (sec) phase (deg) magnitude (db) third order low-pass butterworth figure 74. filter plot for output filter for sd, 8 oversampling
rev. a adv7304a/adv7305a C50C 600r 1.8k 6.8pf 300r dac o/p 75r bnc o/p 6.8 h 2.2 h 18pf 300r figure 75. example of output for output filter for ps, 4 oversampling circuit frequency response ?hz ?0 10m 0n ?40 5n ?20 10n 0 15n 120 20n 240 25n 360 30n 480 ?0 ?0 ?0 ?0 ?0 0 group delay (sec) phase (deg) magnitude (db) 100m fourth order low-pass butterworth figure 76. filter plot for output filter for ps, 4 oversampling 500r 33pf dac o/p 75r bnc o/p 470nh 220nh 82pf 500r 75r 300r figure 77. example for output filter hdtv, 2 oversampling circuit frequency response ?mhz ?0.0 110 100 0n ?03 2n ?02 4n 0 6n 97.6 8n 198 10n 298 12n 398 ?1.4 ?2.9 ?4.3 ?5.7 ?.6 0 magnitude (db) group delay (sec) phase (deg) fourth order low-pass butterworth 14n 498 ?7.1 figure 78. filter plot for output filter for hdtv, 2 oversampling table xxiv. possible output rates input mode pll addr 01h, bits 6? addr 00h, bit 1 output rate sd off 27 mhz (2 ) on 108 mhz (8 ) ps off 27 mhz (1 ) on 108 mhz (4 ) hdtv off 74.25 mhz (1 ) on 148.5 mhz (2 ) sd and off 27 mhz (2 ) on 108 mhz (8 ) ps off 27 mhz (1 ) on 108 mhz (4 ) sd * and off 27 mhz (2 ) on 108 mhz (8 ) hdtv off 74.25 mhz (1 ) on 74.25 mhz (1 ) sd and off 27 mhz (2 ) on 27 mhz (2 ) hdtv * off 74.25 mhz (1 ) on 148.5 mhz (2 ) * oversampled pcb board layout considerations the adv7304a/adv7305a is optimally designed for lowest noise performance, both radiated and conducted noise. to complement the excellent noise performance of the adv7304a/ adv7305a, it is imperative that great care be given to the pc board layout. the layout should be optimized for the lowest noise on the adv7304a/adv7305a power and ground lines. this can be achieved by shielding the digital inputs and provid- ing good decoupling. the lead length between groups of v aa and agnd, v dd and dgnd, and v dd_io and gnd_io pins should be kept as short as possible to minimize inductive ringing. it is recommended that a four-layer printed circuit board be used with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. placement of components should take into account noisy cir- cuits, such as crystal clocks, high speed logic circuitry, and analog circuitry. there should be a separate analog ground plane and a separate digital ground plane. power planes should encompass a digital and an analog power plane. the analog power plane should contain the dacs and all associated circuitry, v ref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead. dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than three inches). the dac termination resistors should be placed as close as possible to the dac outputs and should overlay the pcb s ground plane. as well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry.
rev. a adv7304a/adv7305a ?51? to avoid crosstalk between the dac outputs, it is recommended to leave as much space as possible between the tracks of the individual dac output pins. supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 0.1 ? ? ? ? ? ?
rev. a adv7304a/adv7305a ?52? appendix a copy generation management system hd cgms data registers 2e0 [subaddress 12h] hd cgms is available in 525 p mode only, conforming to cgms-a eia-j cpr1204-1, transfer method of video id information using vertical blanking interval (525 p system), march 1998 and iec61880, 1998, video systems (525/60)? video and accompanied data using the vertical blanking interval?analog interface. when hd cgms is enabled, cgms data is inserted on line 41. the hd cgms data registers are to be found at addresses 21h, 22h, and 23h. c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence 21.2 s 0.22 s 22t ref 5.8 s 0.15 s 6t 0mv e300mv 70% 10% bit 1 t = 1/(f h 33) = 963ns f h = horizontal scan frequency t 30ns + 700mv bit 20 figure 80. cgms waveform sd cgms data registers 2e0 [subaddresses 59h, 5ah, and 5bh] the adv7304a/adv7305a supports copy generation man- agement system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of the even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the adv7304a/adv7305a is config- ured in ntsc mode. the cgms data is 20 bits long; the function of each of these bits is as shown below. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit, see figure 81. if sd cgms crc [address 59h, bit 4] is set to a logic 1, the last six bits, c19ec14, that comprise the 6-bit crc check sequence are calculated automatically on the adv7304a/ adv7305a based on the lower 14 bits (c0ec13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial: xx 6 1 ++ () ( ) = = = = ( ) ? ? ? ? + + ? ?
rev. a adv7304a/adv7305a ?53? appendix b sd wide screen signalling [subaddresses 59h, 5ah, and 5bh] the adv7304a/adv7305a supports wide screen signalling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the adv7304a/ adv7305a is configured in pal mode. the wss data is 14 bits long. the function of each of these bits is shown in table xxvi. the wss data is preceded by a run-in sequence and a start code ( see figure 82). if sd wss [address 59h, bit 7] is set to a logic 1 , it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 ) = = = = = = = = = = = = ? ? ?
rev. a adv7304a/adv7305a ?54? appendix c sd closed captioning [subaddresses 51he54h] the adv7304a/adv7305a supports closed captioning con- forming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of the even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase-locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by a logic level 1 start bit. sixteen bits of data follow the start bit. these consist of two 8-bit bytes, 7 data bits, and 1 odd parity bit. the data for these bytes is stored in the sd closed captioning registers [addresses 53he54h]. the adv7304a/adv7305a also supports the extended closed captioning operation that is active during even fields and is encoded on line 284. the data for this operation is stored in the sd closed captioning registers [addresses 51he52h]. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the adv7304a/ adv7305a. all pixels inputs are ignored during lines 21 and 284 if closed captioning is enabled. fcc code of federal regulations (cfr) 47, section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the adv7304a/adv7305a uses a single buffering method. this means that the closed captioning buffer is only one byte deep; therefore, there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. the data must be loaded one line before (line 20 or line 283) it is output on line 21 and line 284. a typical implementation of this method is to use vsync l tv h w s t a r t p a r t y p a r t y cycles h clck rnn reerence clr brst cycles reency sc h aplte re re re byte byte tw bt party asc characters ata c c w ntsc
rev. a adv7304a/adv7305a ?55? appendix d test patterns the adv7304a/adv7305a can generate sd and hd test patterns. figure 87. pal color bars figure 88. pal black bar (?21 mv, 0 mv, +3.5 mv, +7 mv, +10.5 mv, +14 mv, +18 mv, +23 mv) figure 89. 625 p hatch pattern figure 84. ntsc color bars figure 85. ntsc black bar (?21 mv, 0 mv, +3.5 mv, +7 mv, +10.5 mv, +14 mv, +18 mv, +23 mv) figure 86. 525 p hatch pattern
rev. a adv7304a/adv7305a ?56? figure 90. 525 p field pattern figure 91. 525 p black bar (?35 mv, 0 mv, +7 mv, +14 mv, +21 mv, +28 mv, +35 mv) figure 92. 625 p field pattern figure 93. 625 p black bar (?35 mv, 0 mv, +7 mv, +14 mv, +21 mv, +28 mv, +35 mv)
rev. a adv7304a/adv7305a ?57? table xxviii. ntsc cvbs output on dac a subaddress register setting 00h 82h 11h 01h 40h 10h 42h 40h 44h 40h 4ah 08h 4ch 16h 4dh 7ch 4eh f0h 4fh 21h all other registers are set to 00h. for pal cvbs output on dac a, the same settings in table xxviii are used except those listed in table xxix. table xxix. pal cvbs output on dac a subaddress register setting 40h 11h 4ch cbh 4dh 8ah 4eh 09h 4fh 2ah table xxx. ntsc black bar pattern output on dac a subaddress register setting 00h 82h 02h 04h 11h 01h 40h 10h 42h 40h 44h 40h 4ah 08h 4ch 16h 4dh 7ch 4eh f0h 4fh 21h all other registers are set to 00h. the subcarrier frequency registers 4che4fh will be needed to generate the correct color burst signal. for pal black bar pattern output on dac a, the same set- tings in table xxx are used except those listed in table xxxi. table xxxi. pal black bar pattern output on dac a subaddress register setting 40h 11h 4ch cbh 4dh 8ah 4eh 09h 4fh 2ah table xxxii. 525 p hatch pattern on dac d subaddress register setting 00h 12h 01h 10h 02h 20h 10h 40h 11h 05h 16h a0h 17h 80h 18h 80h all other registers are set to 00h. for a 625 p hatch pattern on dac d, the same settings in table xxxii are used except for subaddress 10h, which has a register setting of 50h. table xxxiii. 525 p field pattern * subaddress register setting 00h 12h 01h 10h 02h 20h 10h 40h 11h 0dh 16h a0h 17h 80h 18h 80h all other registers are set to 00h. * see figure 90. for a 625 p field pattern on dac d, the same settings in table xxxiii are used except for subaddress 10h, which has a register setting of 50h. for a 525 p black bar pattern output on dac d, the same settings in table xxxiii are used except for subaddresses 02h, which has a register setting of 24h. for a 625 p black bar pattern output on dac d, the same settings in table xxxiii are used except for subaddresses 02h and 10h, which have register settings of 24h and 50h, respectively.
rev. a adv7304a/adv7305a ?58? appendix e sd timing modes [subaddress 4ah] mode 0 (ccir-656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7304a/adv7305a is controlled by the start active video (sav) and end active video (eav) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. s_vsync s_hsync s_blank b y c y y a b a b a b y c y c c y c y c eav ce sav ce ancllary ata hanc clck clck clck clck clck clck clck clck en actve ve lne start actve ve lne anal ve npt pels ntscpal syste pal syste y lnesh lnesh s s ccr t r tr t avaava h v sav eav ccr t h b s_hsync v b s_blank b s_vsync splay splay vertcal blank el even el h v el even el splay splay vertcal blank h v s ntsc
rev. a adv7304a/adv7305a ?59? 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 figure 96. sd master mode 0, pal analog video h f v figure 97. sd master mode 0 data transitions
rev. a adv7304a/adv7305a ?60? mode 1: slave option hsync blank l avaava synclal hsync t blank w blank avaav a ccr hsync s_hsync blank s_blank el s_vsync el even el splay splay vertcal blank splay splay vertcal blank el even el el h sync b lank el hsync blank s s ntsc splay vertcal blank el even el el splay splay vertcal blank el even el splay hsync blank el h sync b lank s s pal
rev. a adv7304a/adv7305a ?61? mode 1: master option hsync blank l avaava syncla l hsync t w blank avaava ccr p hsync s_hsync blank s_blank el s_vsync el pel ata pal clck ntsc clck pal clck ntsc clck c y c y hsync blank s t e t s
rev. a adv7304a/adv7305a ?62? mode 2: slave option hsync vsync blank avaava synca hsync vsync a vsync hsync t blank w blank avaava ccr hsync s_hsync blank s_blank el s_vsync splay splay vertcal blank el even el el even el splay splay vertcal blank hsync blank vsync hsync blank vsync s s ntsc splay vertcal blank el even el hsync blank vsync splay splay vertcal blank el even el splay hsync blank vsync s s pal
rev. a adv7304a/adv7305a ?63? mode 2: master option hsync vsync blank avaava synca hsync vsync a vsync hsync t blank w blank avaava ccr hsync s_hsync blank s_blank el s_vsync pal clck ntsc clck pal clck ntsc clck c y c y hsync vsync b lank pel ata s t e t s pal clck ntsc clck pal clck ntsc clck hsync vsync b lank pel ata pal clck ntsc clck c y c y c s t e t s
rev. a adv7304a/adv7305a ?64? mode 3: master/slave option hsync blank l avaava sync l a l hsync t blank w blank avaava ccr hsync s_hsync blank s_blank el s_vsync el even el splay splay vertcal blank splay splay vertcal blank el even el hsync blank el hsync blank el s t ntsc splay vertcal blank el even el hsync blank el splay splay vertcal blank el even el hsync blank el splay s t pal
rev. a adv7304a/adv7305a ?65? appendix f video output levels input code 940 64 eia-770.2, standard for y + 700mv output voltage 0mv e300mv video active 960 64 eia-770.2, standard for pr/pb + 350mv output voltage 0mv e300mv video active 512 e350mv figure 107. eia-770.2 standard output signals (525 p) input code 940 64 eia-770.1, standard for y + 714mv output voltage 0mv e286mv video active 960 64 eia-770.1, standard for pr/pb + 350mv output voltage 0mv e300mv video active 512 + 782mv e350mv figure 108. eia-770.1 standard output signals (525 p) input code 940 64 eia-770.3, standard for y + 700mv output voltage 0mv e300mv video active + 300mv 960 64 eia-770.3, standard for pr/pb + 350mv output voltage 0mv e350mv video active 512 e300mv + 300mv figure 109. eia-770.3 standard output signals (1080 i, 720 p) input code 1023 64 yeoutput levels for full i/p selection + 700mv output voltage 0mv e300mv video active 1023 64 pr/pbeoutput levels for full i/p selection + 700mv output voltage e300mv video active 0mv input code figure 110. output levels for full input selection
rev. a adv7304a/adv7305a ?66? appendix g video standards f v h * f f 272t 4t 4t 1920t eav code sav code digital active line 4 clock 4 clock 2112 2116 2156 2199 0 44 188 192 2111 0 0 0 0 0 0 0 0 f f f v h * c b c r c r y y input pixels analog waveform sample number fvh * = fvh and parity bits sav/eav: line 1e562: f = 0 sav/eav: line 563e1125: f = 1 sav/eav: line1e20; 561e583; 1124e1125: v = 1 sav/eav: line 21e560; 584e1123: v = 0 smpte274m digital horizontal blanking ancillary data (optional) or blanking code 0 h datum figure 111. eav/sav input data timing diagram, smpte274m y eav code ancillary data (optional) sav code digital active line 719 723 736 799 853 0 fvh * = fvh and parity bits sav: line 43e525 = 200h sav: line 1e42 = 2ac eav: line43e525 = 274h eav: line 1e42 = 2d8 4 clock 4 clock 857 719 0 h datum digital horizontal blanking 0 0 0 0 0 0 0 0 c b c r c r y y f v h * smpte293m input pixels analog waveform sample number f f f f f v h * figure 112. eav/sav input data timing diagram, smpte293m
rev. a adv7304a/adv7305a ?67? vertical blank 522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 43 44 42 active video active video figure 113. smpte293m vertical blank active video active video 622 623 624 625 1 2 5 6 7 8 9 12 13 10 11 43 44 45 4 figure 114. itu-r.bt1358 (625 p) 747 748 749 750 1 2 5 6 7 8 26 27 25 744 745 4 display 3 vertical blanking interval figure 115. smpte296m (720 p) vertical blanking interval display 1124 1125 1 2 5 6 7 8 21 4 3 20 22 560 field 1 vertical blanking interval display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 field 2 figure 116. smpte274m (1080 i)
rev. a c02864??1/02(a) printed in u.s.a. adv7304a/adv7305a ?8 outline dimensions 64-lead thin plastic quad flatpack [lqfp] (st-64b) dimensions shown in millimeters top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc 1.60 max seating plane 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw seating plane 12.00 bsc compliant to jedec standards ms-026bcd revision history location page 11/02?ata sheet changed from rev. 0 to rev. a. changes to figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 added thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to table xii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 changes to table xiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 changes to the realtime control, subcarrier reset, timing reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 changes to sd subcarrier frequency registers [subaddress 4ch?fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 changes to figure 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 changes to figure 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 changes to figure 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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